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? 2011-2012 microchip technology inc. advance information ds41620c-page 1 this document includes the programming specifications for the following devices: 1.0 overview the devices can be programmed using either the high- voltage in-circuit serial programming? (icsp?) method or the low-voltage icsp? method. when using low-voltage icsp? programming (lvp = 1 ), the icspdat/icspclk functions are additionally enabled on the ra0/ra1 port pins. this legacy programming feature provides compatibility support for existing pic18f1xk50 designs. for new designs, using the icspdat/icspclk functions on the rc0/rc1 port pins is recommended. for legacy programming support, refer to section 4.2.1 ?legacy icsp pinout programming? . 1.1 hardware requirements 1.1.1 high-voltage icsp programming in high-voltage icsp? mode, these devices require two programmable power supplies: one for v dd and one for the mclr /v pp pin. 1.1.2 low-voltage icsp programming in low-voltage icsp? mode, these devices can be programmed using a single v dd source in the operating range. the mclr /v pp pin does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. 1.1.2.1 single-supply icsp programming the lvp bit in configuration word 2 enables single- supply (low-voltage) icsp programming. the lvp bit defaults to a ? 1 ? (enabled) from the factory. the lvp bit may only be programmed to ? 0 ? by entering the high- voltage icsp mode, where the mclr /v pp pin is raised to v ihh . once the lvp bit is programmed to a ? 0 ?, only the high-voltage icsp mode is available and only the high-voltage icsp mode can be used to program the device. ? pic16f1454 ? pic16lf1454 ? PIC16F1455 ? pic16lf1455 ? pic16f1459 ? pic16lf1459 note 1: the high-voltage icsp mode is always available, regardless of the state of the lvp bit, by applying v ihh to the mclr / v pp pin. 2: while in low-voltage icsp mode, mclr is always enabled, regardless of the mclre bit, and the port pin can no longer be used as a general purpose input. pic16(l)f145x memory pr ogramming specification pic16(l)f145x
pic16(l)f145x ds41620c-page 2 advance information ? 2011-2012 microchip technology inc. 1.2 pin utilization five pins are needed for icsp? programming. it is recommended to use the pins listed in table 1-1 . for pic18f1xk50 legacy designs refer to section 4.2.1 ?legacy icsp pino ut programming? . table 1-1: recommended pin descriptions during programming pin name during programming function pin type pin description rc1 icspclk i clock input ? schmitt trigger input rc0 icspdat i/o data input/output ? schmitt trigger input mclr /v pp /ra3 program/verify mode p (1) program mode select/programming power supply v dd v dd p power supply v ss v ss p ground legend: i = input, o = output, p = power note 1: the programming high voltage is internally generated. to ac tivate the program/verify mode, high voltage needs to be applied to mclr input. since the mclr is used for a level source, mclr does not draw any significant current.
? 2011-2012 microchip technology inc. advance information ds41620c-page 3 pic16(l)f145x 2.0 device pinouts the pin diagrams are shown in figure 2-1 through figure 2-4 . the pins that are required for programming are listed in table 1-1 and shown in bold lettering in the pin diagrams. figure 2-1: 14-pin pdip, soic, t ssop diagram for pi c16(l)f1454/1455 figure 2-2: 16-pin qfn diag ram for pic16(l)f1454/1455 pdip, soic, tssop pic16(l)f1454/1455 1 2 3 4 14 13 12 11 5 6 7 10 9 8 v dd ra5 ra4 mclr /v pp /ra3 rc5 rc4 rc3 v ss ra0/d+/icspdat (1) ra1/d-/icspclk (1) v usb3v3 rc0/icspdat rc1/icspclk rc2 note 1: lvp support for pic18(l)f1xk50 legacy designs. 78 2 3 1 11 12 5 9 10 13 14 15 16 6 4 ra5 ra4 mclr /v pp /ra3 rc4 rc3 icspclk/rc1 rc2 rc0/icspdat ra0/d+/icspdat (1) v usb3v3 ra1/d-/icspclk (1) vss v dd nc rc5 nc pic16(l)f1454/1455 qfn (4x4) note 1: lvp support for pic18(l)f1xk50 legacy designs.
pic16(l)f145x ds41620c-page 4 advance information ? 2011-2012 microchip technology inc. figure 2-3: 20-pin pdip, soic, ssop diagram for pic16(l)f1459 figure 2-4: 20-pin qfn di agram for pic16(l)f1459 pic16(l)f1459 1 2 3 4 14 13 12 11 5 6 7 10 9 8 v dd ra5 ra4 mclr /v pp /ra3 rc5 rc4 v ss ra0/d+/icspdat (1) ra1/d-/icspclk (1) v usb3v3 rc0/icspdat rc1/icspclk rc2 rc3 pdip, soic, ssop note 1: lvp support for pic18(l)f1xk50 legacy designs. 18 17 16 15 20 19 rc6 rc7 rb7 rb4 rb5 rb6 89 2 3 1 14 15 16 10 11 6 12 13 17 18 19 20 7 5 4 pic16(l)f1459 mclr /v pp /ra3 rc5 rc4 rc3 rc6 rc7 rb7 rb4 rb5 rb6 rc1/icspclk rc0/icspdat v usb 3 v 3 ra1/d-/icspclk (1) ra0/d+/icspdat (1) vss v dd ra4 ra5 rc2 qfn (4x4) note 1: lvp support for pic18(l)f1xk50 legacy designs.
? 2011-2012 microchip technology inc. advance information ds41620c-page 5 pic16(l)f145x 3.0 memory map the memory is broken into two sections: program memory and configuration memory. only the size of the program memory changes between devices, the configuration memory remains the same. figure 3-1: pic16(l)f1454/1455/1459 program memory mapping 7fff h 8000 h 8200 h ffff h 8 kw implemented maps to program memory configuration memory 8000-81ffh user id location user id location user id location user id location reserved revision id device id configuration word 1 configuration word 2 calibration word 1 calibration word 2 reserved 8000h 8001h 8002h 8003h 8004h 8005h 8006h 8007h 8009h 8008h 800ah implemented 0000h maps to 0-1fffh 1fffh 800bh-81ffh
pic16(l)f145x ds41620c-page 6 advance information ? 2011-2012 microchip technology inc. 3.1 user id location a user may store identification information (user id) in four designated locations. the user id locations are mapped to 8000h-8003h. each location is 14 bits in length. code protection has no effect on these memory locations. each locati on may be read with code protection enabled or disabled. 3.2 revision id the revision id word is located at 8005h. this location is read-only and cannot be erased or modified. register 3-1: revision id ? 8005h (1) note: mplab ? ide only displays the seven least significant bits (lsb) of each user id location, the upper bits are not read. it is recommended that only the seven lsbs be used if mplab ide is the primary tool used to read these addresses. rrrrrr rev<13:8> bit 13 bit 8 r r rrrrrr rev<7:0> bit 7 bit 0 legend: r = readable bit bit 13-0 rev<13:0>: revision id bits these bits are used to identify the revision. note 1: this location cannot be written.
? 2011-2012 microchip technology inc. advance information ds41620c-page 7 pic16(l)f145x 3.3 device id the device id word is located at 8006h. this location is read-only and cannot be erased or modified. table 3-1: device id values register 3-2: device id: device id register (1) rrrrrr dev<13:8> bit 13 bit 8 rrrrrrrr dev<7:0> bit 7 bit 0 legend: r = readable bit bit 13-0 dev<13:0>: device id bits these bits are used to identify the part number. note 1: this location cannot be written. device device id values dev<13:0> pic16f1454 0011 0000 0010 0000 (3020h) pic16lf1454 0011 0000 0010 0100 (3024h) PIC16F1455 0011 0000 0010 0001 (3021h) pic16lf1455 0011 0000 0010 0101 (3025h) pic16f1459 0011 0000 0010 0011 (3023h) pic16lf1459 0011 0000 0010 0111 (3027h)
pic16(l)f145x ds41620c-page 8 advance information ? 2011-2012 microchip technology inc. 3.4 configuration words there are two configuration words, configuration word 1 (8007h) and configuration word 2 (8008h). the individual bits within these configuration words are used to enable or disable device functions such as the brown-out reset, code protecti on and power-up timer. 3.5 calibration words the internal calibration values are factory calibrated and stored in calibration words 1 and 2 (8009h, 800ah). the calibration words do not participate in erase operations. the device can be erased without affecting the calibration words.
? 2011-2012 microchip technology inc. advance information ds41620c-page 9 pic16(l)f145x register 3-3: configuration word 1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 u-1 fcmen ieso clkouten boren<1:0> ? bit 13 bit 8 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 cp mclre pwrte wdte<1:0> fosc<2:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit -n = value after bulk erase ?1? = bit is set ?0? = bit is cleared bit 13 fcmen: fail-safe clock monitor enable bit 1 = fail-safe clock monitor is enabled 0 = fail-safe clock monitor is disabled bit 12 ieso: internal/external switchover bit 1 = internal/external switchover mode is enabled 0 = internal/external switchover mode is disabled bit 11 clkouten : clock out enable bit 1 = clkout function is disabled. i/o or oscillator function on clkout pin. 0 = clkout function is enabled on clkout pin bit 10-9 boren<1:0>: brown-out reset enable bits (1) 11 = bor enabled 10 = bor enabled during operation and disabled in sleep 01 = bor controlled by sboren bit of the pcon register 00 = bor disabled bit 8 unimplemented: read as ? 1 ? bit 7 cp : code protection bit (2) 1 = program memory code protection is disabled 0 = program memory code protection is enabled bit 6 mclre: mclr /v pp pin function select bit if lvp bit = 1 : this bit is ignored. if lvp bit = 0 : 1 =mclr /v pp pin function is mclr ; weak pull-up enabled. 0 =mclr /v pp pin function is digital input; mclr internally disabled; weak pull-up under control of wpua register. bit 5 pwrte : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled bit 4-3 wdte<1:0>: watchdog timer enable bit 11 = wdt enabled 10 = wdt enabled while running and disabled in sleep 01 = wdt controlled by the swdt en bit in the wdtcon register 00 = wdt disabled bit 2-0 fosc<2:0>: oscillator selection bits 111 = ech: external clock, hi gh-power mode: on clkin pin 110 = ecm: external clock, medium-power mode: on clkin pin 101 = ecl: external clock, low-power mode: on clkin pin 100 = intosc oscillator: i/o function on osc1 pin 011 = extrc oscillator: rc function on clkin pin 010 = hs oscillator: high-speed crystal/resonator on osc1 and osc2 pins 001 = xt oscillator: crystal/resonator on osc1 and osc2 pins 000 = lp oscillator: low-power crystal on osc1 and osc2 pins note 1: enabling brown-out reset does not automatically enable power-up timer. 2: once enabled (cp = 0 ), code protection can only be disabled by bulk erasing the device.
pic16(l)f145x ds41620c-page 10 advance information ? 2011-2012 microchip technology inc. register 3-4: configuration word 2 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 lvp debug lpbor borv stvren pllen bit 13 bit 8 r/p-1 r/p-1 r/p-1 r/p-1 u-1 u-1 r/p-1 r/p-1 pllmult usblsclk cpudiv<1:0> ? ?wrt<1:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit -n = value after bulk erase ?1? = bit is set ?0? = bit is cleared bit 13 lvp: low-voltage programming enable bit (1), (2) 1 = low-voltage programming enabled 0 = hv on mclr /v pp must be used for programming bit 12 debug : debugger mode bit 1 = in-circuit debugger disabled, icspclk and icspdat pins are general purpose i/o pins 0 = in-circuit debugger enabled, icspclk and icspdat pins are dedicated to the debugger bit 11 lpbor : low-power bor bit 1 = low-power bor is disabled 0 = low-power bor is enabled bit 10 borv: brown-out reset voltage selection bit 1 = brown-out reset voltage (v bor ), low trip point selected 0 = brown-out reset voltage (v bor ), high trip point selected bit 9 stvren: stack overflow/underfl ow reset enable bit 1 = stack overflow or underflow will cause a reset 0 = stack overflow or underflow will not cause a reset bit 8 pllen: pllen enable bit 1 = pll enabled 0 = pll disabled bit 7 pllmult: pll multiplier selection bit 1 = 3x pll output frequency is selected 0 = 4x pll output frequency is selected bit 6 usblsclk: usb low-speed clock selection bit 1 = usb clock divide-by 8, (48 mhz system input clock expected) 0 = usb clock divide-by 4, (24 mhz system input clock expected) bit 5-4 cpudiv<1:0>: cpu system clock selection bits 11 = cpu system clock divided by 6 10 = cpu system clock divided by 3 01 = cpu system clock divided by 2 00 = no cpu system clock divide. bit 3-2 unimplemented: read as ? 1 ? bit 1-0 wrt<1:0>: flash memory self-write protection bits 8 k w flash memory ( pic16(l)f1454/1455/1459) : 11 = write protection off 10 = 0000h to 01ffh write-protected, 0200h to 1fffh may be modified by pmcon control 01 = 0000h to 0fffh write-protected, 1000h to 1fffh may be modified by pmcon control 00 = 0000h to 1fffh write-protected, no addresses may be modified by pmcon control note 1: the lvp bit cannot be programmed to ? 0 ? when programming mode is entered via lvp. 2: when lvp = 1 , the icsp? functions are enabled on the icspdat/d+/ra0 and icspclk/d-/ra1 pins.
? 2011-2012 microchip technology inc. advance information ds41620c-page 11 pic16(l)f145x 4.0 program/verify mode in program/verify mode, th e program memory and the configuration memory can be accessed and programmed in serial fashion. icspdat and icspclk are used for the data and the clock, respectively. all commands and data words are transmitted lsb first. data changes on the rising edge of the icspclk and latched on the falling edge. in program/verify mode both the icspdat and icspclk are schmitt trigger inputs. the sequence that enters the device into program/verify mode places all other logic into the reset state. upon entering program/verify mode, all i/os are automatically configured as high-impedance inputs and the address is cleared. 4.1 high-voltage program/verify mode entry and exit there are two different me thods of entering program/ verify mode via high-voltage: ?v pp ? first entry mode ?v dd ? first entry mode 4.1.1 v pp ? first entry mode to enter program/verify mode via the v pp -first method the following sequence must be followed: 1. hold icspclk and icspdat low. all other pins should be unpowered. 2. raise the voltage on mclr from 0v to v ihh . 3. raise the voltage on v dd from 0v to the desired operating voltage. the v pp -first entry prevents t he device from executing code prior to entering program/verify mode. for example, the device will execute code when configuration word 1 has mclr disabled (mclre = 0 ), the power-up timer is disabled (pwrte = 0 ), the internal oscillator is selected (f osc = 100 ), and icspclk and icspdat pins are driven by the user application. since this may prevent entry, v pp -first entry mode is strongly recommended. see the timing diagram in figure 8-2 . 4.1.2 v dd ? first entry mode to enter program/verify mode via the v dd -first method the following sequence must be followed: 1. hold icspclk and icspdat low. 2. raise the voltage on v dd from 0v to the desired operating voltage. 3. raise the voltage on mclr from v dd or below to v ihh . the v dd -first method is useful when programming the device when v dd is already applied, for it is not necessary to disconnect v dd to enter program/verify mode. see the timing diagram in figure 8-1 . 4.1.3 program/verify mode exit to exit program/verify mode take mclr to v dd or lower (v il ). see figures 8-3 and 8-4 . 4.2 low-voltage programming (lvp) mode the low-voltage programming mode allows devices to be programmed using v dd only, without high voltage. when the lvp bit of configuration word 2 register is set to ? 1 ?, the low-voltage icsp programming entry is enabled. to disable the low-voltage icsp mode, the lvp bit must be programmed to ? 0 ?. this can only be done while in the high-voltage entry mode. entry into the low-voltage icsp program/verify modes requires the following steps: 1. mclr is brought to v il . 2. a 32-bit key sequence is presented on icspdat, while clocking icspclk. the key sequence is a sp ecific 32-bit pattern, '0100 1101 0100 0011 0100 1000 0101 0000' (more easily remembered as mchp in ascii). the device will enter program/verify mode only if the sequence is valid. the least significant bit (lsb) of the least significant nibble must be shifted in first. once the key sequence is complete, mclr must be held at v il for as long as program/verify mode is to be maintained. for low-voltage programming timing, see figure 8-8 and figure 8-9 . exiting program/verify mode is done by no longer driving mclr to v il . see figure 8-8 and figure 8-9 . note: to enter lvp mode, the lsb of the least significant nibble must be shifted in first. this differs from entering the key sequence on other parts.
pic16(l)f145x ds41620c-page 12 advance information ? 2011-2012 microchip technology inc. 4.2.1 legacy icsp pinout programming the legacy icsp pinout is for use with designs based on previous pic18f1xk50 20-pin parts. this allows the programming through the same pinout layout. if lvp = 1 , the pic ? device can be programmed through the recommended pins or the legacy pins (refer to table 4-1 ). when lvp is set, entry into the low-voltage icsp program/verify mode, as well as the programming method, is the same as discussed in section 4.2 ?low-voltage programming (lvp) mode? . however, both the legacy and recommended icspdat are monitored while clocking icspclk. whichever icspdat first receives the 32-bit key sequence will be used for programming with its corresponding icspclk. table 4-1: legacy pin descri ptions during programming figure 4-1: in-circuit programming (icsp) recommended method note: the v ih voltage levels on port pins ra0/icspdat/d+ and ra1/icspclk/d- must be limited to 3. 3v maximum, due to usb circuitry. the device must not be attached to a usb host and the usb mod- ule must be disabled. refer to figure 4-1 , figure 4-2 and figure 4-3 . pin name during programming function pin type pin description ra1 icspclk i clock input ? schmitt trigger input ra0 icspdat i data input ? schmitt trigger input mclr /v pp /ra3 program/verify mode p (1) program mode select/programming power supply v dd v dd p power supply v ss v ss p ground legend: i = input, o = output, p = power note 1: the programming high voltage is internally generated. to ac tivate the program/verify mode, high voltage needs to be applied to mclr input. since the mclr is used for a level source, mclr does not draw any significant current. application programmer v pp +5v v ss icspdat icspclk v ss rc0/ icspdat rc1/ icspclk pic ? usb mcu mclr/v pp /ra3 v dd
? 2011-2012 microchip technology inc. advance information ds41620c-page 13 pic16(l)f145x figure 4-2: in-circuit programming (icsp) legacy with translator figure 4-3: in-circuit pr ogramming (icsp) legacy a1 a2 v2 y1 y2 v1 bidirectional level translator application translator programmer v dd v pp +5v v ss icspdat icspclk v ss ra0/ icspdat (1) /d+ ra1/ icspclk (1) /d- pic ? usb mcu mclr / v pp /ra3 for use with f devices v dd > 3.3v only application programmer v dd v pp +3v v ss icspdat icspclk v ss ra0/d+/ icspdat (1) ra1/d-/ icspclk (1) pic ? usb mcu for use with all lf devices or f devices v dd < 3.3v only mclr / v pp /ra3
pic16(l)f145x ds41620c-page 14 advance information ? 2011-2012 microchip technology inc. 4.3 program/verify commands the devices implement ten programming commands; each six bits in length. the commands are summarized in table 4-2 . commands that have data associated with them are specified to have a minimum delay of t dly between the command and the data. after this delay 16 clocks are required to either clock in or clock out the 14-bit data word. the first clock is for the start bit and the last clock is for the stop bit. 4.3.1 load configuration the load configuration command is used to access the configuration memory (user id locations, configuration words, calibration words). the load configuration command sets the address to 8000h and loads the data latches with one word of data (see figure 4-4 ). after issuing the load configuration command, use the increment address command until the proper address to be programmed is reached. the address is then pro- grammed by issuing either the begin internally timed programming or begin externally timed programming command. the only way to get back to the program memory (address 0) is to exit program/verify mode or issue the reset address command after the configuration memory has been accessed by the load configuration command. figure 4-4: load configuration table 4-2: command mapping command mapping data/note binary (msb ? lsb) hex load configuration x00000 00h 0 , data (14), 0 load data for program memory x00010 02h 0 , data (14), 0 read data from program memory x00100 04h 0 , data (14), 0 increment address x00110 06h ? reset address x10110 16h ? begin internally timed programming x01000 08h ? begin externally timed programming x11000 18h ? end externally timed programming x01010 0ah ? bulk erase program memory x01001 09h internally timed row erase program memory x10001 11h internally timed note: externally timed writes are not supported for configuration and calibration bits. any externally timed write to the configuration or calibration word will have no effect on the targeted word. x 0 0 lsb msb 0 1 2 3 4 5 6 1 2 15 16 icspclk icspdat 000 0 t dly
? 2011-2012 microchip technology inc. advance information ds41620c-page 15 pic16(l)f145x 4.3.2 load data for program memory the load data for program memory command is used to load one 14-bit word into the data latches. the word programs into program memory after the begin internally timed program ming or begin externally timed programming command is issued (see figure 4-5 ). figure 4-5: load data for program memory 4.3.3 read data from program memory the read data from program memory command will transmit data bits out of the program memory map currently accessed, starting with the second rising edge of the clock input. the icspdat pin will go into output mode on the first falling clock edge, and it will revert to input mode (high-impedance) after the 16th falling edge of the clock. if the program memory is code-protected (cp ), the data will be read as zeros (see figure 4-6 ). figure 4-6: read data from program memory icspclk icspdat 1 2 3 4 5 6 1 2 15 16 x 0 0 lsb msb 0 010 0 t dly 1 2 3 4 5 6 1 2 15 16 lsb msb t dly icspclk icspdat input input output x (from programmer) x 0 001 0 icspdat (from device)
pic16(l)f145x ds41620c-page 16 advance information ? 2011-2012 microchip technology inc. 4.3.4 increment address the address is incremented when this command is received. it is not possible to decrement the address. to reset this counter, t he user must use the reset address command or exit program/verify mode and re- enter it. if the address is incremented from address 7fffh, it will wrap-around to location 0000h. if the address is incremented from ffffh, it will wrap-around to location 8000h. figure 4-7: increment address 4.3.5 reset address the reset address command will reset the address to 0000h, regardless of the current value. the address is used in program memory or the configuration memory. figure 4-8: reset address x 0 1 23 4 5 6 1 2 icspclk icspdat 0 1 1 3 x x x t dly next command 0 address + 1 address x 0 12 3 4 5 6 1 2 icspclk icspdat 0 1 1 3 x x x t dly next command 1 0000h n address
? 2011-2012 microchip technology inc. advance information ds41620c-page 17 pic16(l)f145x 4.3.6 begin internally timed programming a load configuration or load data for program memory command must be given before every begin programming command. programming of the addressed memory will begin after this command is received. an internal timing mechanism executes the write. the user must allo w for the program cycle time, t pint , for the programming to complete. the end externally timed programming command is not needed when the begin internally timed programming is used to start the programming. the program memory address that is being programmed is not erased prior to being programmed. figure 4-9: begin internally timed programming 4.3.7 begin externally timed programming a load configuration or load data for program memory command must be given before every begin programming command. programming of the addressed memory will begin after this command is received. to complete the programming the end externally timed programming command must be sent in the specified time window defined by t pext (see figure 4-10 ). externally timed writes are not supported for configuration and calibration bits. any externally timed write to the configuration or calibration word will have no effect on the targeted word. figure 4-10: begin externally timed programming 1 2 3 4 5 6 1 2 icspclk icspdat 3 t pint x 1 0 0 0 x x x 0 next command x 1 0 1 23 4 5 6 1 2 icspclk icspdat 0 0 0 1 1 0 end externally timed programming command t pext 3
pic16(l)f145x ds41620c-page 18 advance information ? 2011-2012 microchip technology inc. 4.3.8 end externally timed programming this command is required after a begin externally timed programming command is given. this command must be sent within the time window specified by t pext after the begin externally timed programming command is sent. after sending the end externally timed programming command, an additional delay (t dis ) is required before sending the next command. this delay is longer than the delay ordinarily requ ired between other commands (see figure 4-11 ). figure 4-11: end externally timed programming 4.3.9 bulk erase program memory the bulk erase program memory command performs two different functions dependent on the current state of the address. a bulk erase program memory command should not be issued when the address is greater than 8008h. after receiving the bulk erase program memory command the erase will not complete until the time interval, t erab , has expired. figure 4-12: bulk erase program memory 12 3 4 5 6 1 2 icspclk icspdat 3 t dis x 1 0 1 0 x x x 1 next command address 0000h-7fffh: program memory is erased configuration words are erased address 8000h-8008h: program memory is erased configuration words are erased user id locations are erased note: the code protection configuration bit (cp ) has no effect on the bulk erase program memory command. 1 2 3 4 5 6 1 2 icspclk icspdat 3 t erab x 1 1 0 0 x x x 0 next command
? 2011-2012 microchip technology inc. advance information ds41620c-page 19 pic16(l)f145x 4.3.10 row erase program memory the row erase program memory command will erase an individual row. refer to ta b l e 4 - 3 for row sizes of specific devices and the pc bits used to address them. if the program memory is code-protected, the row erase program memory command will be ignored. when the address is 8000h-8008h, the row erase program memory command will only erase the user id locations, regardless of the setting of the cp configuration bit. after receiving the ro w erase program memory command, the erase will not complete until the time interval, t erar , has expired. figure 4-13: row erase program memory table 4-3: programming row size and latches devices pc row size number of latches pic16(l)f1454 <15:5> 32 32 pic16(l)f1455 <15:5> 32 32 pic16(l)f1459 <15:5> 32 32 1 2 3 4 5 6 1 2 icspclk icspdat 3 t erar x 0 1 0 0 x x x 1 next command
pic16(l)f145x ds41620c-page 20 advance information ? 2011-2012 microchip technology inc. 5.0 programming algorithms the devices use internal latches to temporarily store the 14-bit words used for programming. refer to table 4-3 for specific latch information. the data latches allow the user to write the program words with a single begin externally timed programming or begin internally timed programming command. the load program data or the lo ad configuration command is used to load a single data latch. the data latch will hold the data until the begin externally timed programming or begin internally timed programming command is given. the data latches are aligned with the lsbs of the address. the pc?s address at the time the begin externally timed programming or begin internally timed programming command is given will determine which location(s) in memory are written. writes cannot cross the physical boundary. for example, with the PIC16F1455, attempting to write from address 0002h- 0009h will result in data being written to 0008h-000fh. if more than the maximum number of data latches are written without a begin exte rnally timed programming or begin internally timed programming command, the data in the data latches will be overwritten. the following figures show the recommended flowcharts for programming.
? 2011-2012 microchip technology inc. advance information ds41620c-page 21 pic16(l)f145x figure 5-1: device program/verify flowchart done start bulk erase device write user ids enter programming mode write program memory (1) verify user ids write configuration words (2) verify configuration words exit programming mode verify program memory note 1: see figure 5-2 . 2: see figure 5-5 .
pic16(l)f145x ds41620c-page 22 advance information ? 2011-2012 microchip technology inc. figure 5-2: program memory flowchart start read data program memory data correct? report programming failure all locations done? no no increment address command from bulk erase program yes memory (1, 2) done yes note 1: this step is optional if the dev ice has already been erased or ha s not been previously programmed. 2: if the device is code-protected or must be comp letely erased, then bulk erase the device per figure 5-6 . 3: see figure 5-3 or figure 5-4 . program cycle (3)
? 2011-2012 microchip technology inc. advance information ds41620c-page 23 pic16(l)f145x figure 5-3: one-word program cycle begin programming wait t dis load data for program memory command (internally timed) begin programming wait t pext command (externally timed) (1) end programming wait t pint program cycle command note 1: externally timed writes are not support ed for configuration and calibration bits.
pic16(l)f145x ds41620c-page 24 advance information ? 2011-2012 microchip technology inc. figure 5-4: multiple-word program cycle begin programming wait t pint load data for program memory command (internally timed) wait t pext end programming wait t dis load data for program memory increment address command load data for program memory begin programming command (externally timed) latch 1 latch 2 latch n increment address command program cycle command
? 2011-2012 microchip technology inc. advance information ds41620c-page 25 pic16(l)f145x figure 5-5: configuration memory program flowchart start load configuration program cycle (2) read data memory command data correct? report programming failure address = 8004h? data correct? report programming failure yes no yes yes no increment address command no increment address command done one-word one-word program cycle (2) (config. word 1) increment address command increment address command (user id) from program read data memory command from program program bulk erase memory (1) data correct? report programming failure yes no one-word program cycle (2) (config. word 2) increment address command read data memory command from program note 1: this step is optional if the device is erased or not previously programmed. 2: see figure 5-3 .
pic16(l)f145x ds41620c-page 26 advance information ? 2011-2012 microchip technology inc. figure 5-6: erase flowchart start load configuration done bulk erase program memory note: this sequence does not erase the calibration words.
? 2011-2012 microchip technology inc. advance information ds41620c-page 27 pic16(l)f145x 6.0 code protection code protection is controlled using the cp bit in configuration word 1. when code protection is enabled, all program memory locations (0000h-7fffh) read as ? 0 ?. further programming is disabled for the program memory (0000h-7fffh). the user id locations and configuration words can be programmed and read out regardless of the code protection settings. 6.1 program memory code protection is enabled by programming the cp bit in configuration word 1 register to ? 0 ?. the only way to disable code protection is to use the bulk erase program memory command. 7.0 hex file usage in the hex file there are two bytes per program word stored in the intel ? inhx32 hex format. data is stored lsb first, msb second. because there are two bytes per word, the addresses in the hex file are 2x the address in program memory . (example: configuration word 1 is stored at 8007h on the pic16(l)f1458. in the hex file this will be referenced as 1000eh-1000fh). 7.1 configuration word to allow portability of code , it is strongly recommended that the programmer is abl e to read the configuration words and user id locations from the hex file. if the configuration words information was not present in the hex file, a simple warning message may be issued. similarly, while saving a hex file, configuration words and user id information should be included. 7.2 device id if a device id is present in the hex file at 1000ch- 1000dh (8006h on the part), the programmer should verify the device id against the value read from the part. on a mismatch condition the programmer should generate a warning message.
pic16(l)f145x ds41620c-page 28 advance information ? 2011-2012 microchip technology inc. 7.3 checksum computation the checksum is calculated by two different methods dependent on the setting of the cp configuration bit. 7.3.1 program code protection disabled with the program code protection disabled, the checksum is computed by reading the contents of the program memory locations and adding up the program memory data starting at address 0000h, up to the maximum user addressable location. any carry bit exceeding 16 bits are ignored. additionally, the relevant bits of the configuration words are added to the checksum. all unimplemented configuration bits are masked to ? 0 ?. example 7-1: checksum computed with prog ram code protection disabled (cp = 1 ), pic16f1459, blank device table 7-1: configuration word mask values device config. word 1 mask config. word 2 mask pic16(l)f1454 3effh 3ff3h pic16(l)f1455 3effh 3ff3h pic16(l)f1459 3effh 3ff3h pic16f1459 sum of memory addresses 0000h-1fffh e000h (1) configuration word 1 3fffh (2) configuration word 1 mask 3effh (3) configuration word 2 3fffh (4) configuration word 2 mask 3ff3h (5) checksum = e000h + (3fffh and 3effh) + (3fffh and 3ff3h) (6) = e000h + 3effh + 3ff3h = 5ef2h note 1: this value is obtained by taking the total number of program memory locations (0x000 to 0x1fffh which is e000h) and multiplying it by the blank memory value of 0x3fff to get the sum of 1ff f800h. then, truncate to 16 bits, thus having a final value of f800h. 2: this value is obtained by making all bits of the configuration word 1 a ? 1 ?, then converting it to hex, thus having a value of 3fffh. 3: this value is obtained by making all used bits of the configuration word 1 a ? 1 ?, then converting it to hex, thus having a value of 3effh. 4: this value is obtained by making all bits of the configuration word 2 a ? 1 ?, then converting it to hex, thus having a value of 3fffh. 5: this value is obtained by making all used bits of the configuration word 2 a ? 1 ?, then converting it to hex, thus having a value of 3ff3h. 6: this value is obtained by anding the configuration word value with the configuration word mask value and adding it to the sum of memory addresses: (3ff fh and 3effh) + (3fffh and 3ff3h) + e000h = 1 34feh. then, truncate to 16 bits, thus having a final value of 5ef2h.
? 2011-2012 microchip technology inc. advance information ds41620c-page 29 pic16(l)f145x example 7-2: checksum computed with prog ram code protection disabled (cp = 1 ), pic16lf1459, 00aah at first and last address pic16lf1459 sum of memory addresses 0000h-1fffh 6156h (1) configuration word 1 3fffh (2) configuration word 1 mask 3effh (3) configuration word 2 3fffh (4) configuration word 2 mask 3ff3h (5) checksum = 6156h + (3fffh and 3effh) + (3fffh and 3ff3h) (6) = 6156h + 3effh + 3ff3h = e048h note 1: this value is obtained by taking the total number of program memory locations (0x000 to 0x1fffh which is 2000h) subtracting 2h whic h yields 1effh, then multiplying it by the blank memory value of 0x3fff to get the sum of 7ff 6002h. then, truncate to 16 bits the value of 6002h. now add 00aah (00aah + 00aah) to 6002h to get the final value of 6156h. 2: this value is obtained by making all bits of the configuration word 1 a ? 1 ?, then converting it to hex, thus having a value of 3fffh. 3: this value is obtained by making all used bits of the configuration word 1 a ? 1 ?, then converting it to hex, thus having a value of 3effh. 4: this value is obtained by making all bits of the configuration word 2 a ? 1 ?, then converting it to hex, thus having a value of 3fffh. 5: this value is obtained by making all used bits of the configuration word 2 a ? 1 ?, then converting it to hex, thus having a value of 3ff3h. 6: this value is obtained by anding the configuratio n word value with the configuration word mask value and adding it to the sum of memory addresses: (3 fffh and 3effh) + (3fffh and 3ff3h) + 6156h = e048h. then, truncate to 16 bits, thus having a final value of e048h.
pic16(l)f145x ds41620c-page 30 advance information ? 2011-2012 microchip technology inc. 7.3.2 program code protection enabled with the program code protection enabled, the checksum is computed in the following manner: the least significant nibble of each user id is used to create a 16-bit value. the masked value of user id location 8000h is the most significant nibble. this sum of user ids is summed with the configuration words (all unimplemented configuration bits are masked to ? 0 ?). example 7-3: checksum computed with program code protection enabled (cp = 0 ), pic16f1459, blank device pic16f1459 configuration word 1 3f7fh (1) configuration word 1 mask 3e7fh (2) configuration word 2 3fffh (3) configuration word 2 mask 3ff3h (4) user id (8000h) 0006h (5) user id (8001h) 0007h (5) user id (8002h) 0001h (5) user id (8003h) 0002h (5) sum of user ids = (0006h and 000fh) << 12 + (0007h and 000fh) << 8 + (0001h and 000fh) << 4 + (0002h and 000fh) (6) = 6000h + 0700h + 0010h + 0002h = 6712h checksum = (3f7fh and 3e7fh) + (3ff fh and 3ff3h) + sum of user ids (7) = 3e7fh +3ff3h + 6712h = e584h note 1: this value is obtained by making all bits of the configuration word 1 a ? 1 ?, but the code-protect bit is ? 0 ? (thus, enabled), then converting it to hex, thus having a value of 3f7fh. 2: this value is obtained by making all used bits of the configuration word 1 a ? 1 ?, but the code -protect bit is ? 0 ? (thus, enabled), then converting it to hex, thus having a value of 3e7fh. 3: this value is obtained by making all bits of the configuration word 2 a ? 1 ?, then converting it to hex, thus having a value of 3fffh. 4: this value is obtained by making all used bits of the configuration word 2 a ? 1 ?, then converting it to hex, thus having a value of 3ff3h. 5: these values are picked at random for this example; they could be any 16-bit value. 6: in order to calculate the sum of user ids, take the 16-bit value of the first user id location (0006h), and the address to (000fh), thus masking the msb. this gives you the value 0006h, then shift left 12 bits, giving you 6000h. do the same procedure for the 16-b it value of the second user id location (0007h), except shift left 8 bits. also, do the same for the third user id location (0001h), except shift left 4 bits. for the fourth user id location do not shift. finally, add up all four user id values to get the final sum of user ids of 6712h. 7: this value is obtained by anding t he configuration word value with the configuration word mask value and adding it to the sum of user ids: (3f7fh and 3e7fh) + (3fffh and 3ff3h) + 6712h = e584h. then, truncate to 16 bits, thus having a final value of e584h.
? 2011-2012 microchip technology inc. advance information ds41620c-page 31 pic16(l)f145x example 7-4: checksum computed with program code protection enabled (cp = 0 ), pic16lf1459, 00aah at first and last address pic16lf1459 configuration word 1 3f7fh (1) configuration word 1 mask 3e7fh configuration word 2 3fffh (3) configuration word 2 mask 3ff3h (4) user id (8000h) 000eh (5) user id (8001h) 0008h (5) user id (8002h) 0005h (5) user id (8003h) 0008h (5) sum of user ids = (000eh and 000fh) << 12 + (0008h and 000fh) << 8 + (0005h and 000fh) << 4 + (0008h and 000fh) (6) = e000h + 0800h + 0050h + 0008h = e858h checksum = (3f7fh and 3e7fh) + (3fffh and 3ff3h) + sum of user ids (7) = 3e7fh +3ff3h + e858h = 66cah note 1: this value is obtained by making all bits of the configuration word 1 a ? 1 ?, but the code-p rotect bit is ? 0 ? (thus, enabled), then converting it to hex, thus having a value of 3f7fh. 2: this value is obtained by making all us ed bits of the configuration word 1 a ? 1 ?, but the code-protect bit is ? 0 ? (thus, enabled), then converting it to hex, thus having a value of 3e7fh. 3: this value is obtained by making all bits of the configuration word 2 a ? 1 ?, then converting it to hex, thus having a value of 3fffh. 4: this value is obtained by making all used bits of the configuration word 2 a ? 1 ?, then converting it to hex, thus having a value of 3ff3h. 5: these values are picked at random for this example; they could be any 16-bit value. 6: in order to calculate the su m of user ids, take the 16- bit value of the first user id location (000eh), and the address to (000fh), thus masking the msb. this gives you the value 000eh, then shift left 12 bits, giving you e000h. do the same procedure for the 16-b it value of the second user id location (0008h), except shift left 8 bits. also, do the same for the third user id location (0005h), except shift left 4 bits. for the fourth user id location do not sh ift. finally, add up all four user id values to get the final sum of user ids of e858h. 7: this value is obtained by anding the configuratio n word value with the configuration word mask value and adding it to the sum of user ids: (3f7fh and 3e7fh) + (3fffh and 3ff3h) + e858h = 66cah. then, truncate to 16 bits, thus having a final value of 66cah.
pic16(l)f145x ds41620c-page 32 advance information ? 2011-2012 microchip technology inc. 8.0 electrical specifications refer to the device specif ic data sheet for absolute maximum ratings. table 8-1: ac/dc characteristics timing requirements for program/verify mode ac/dc characteristics standard operating conditions production tested at 25c sym. characteristics min. typ. max. units conditions/comments programming supply voltages and currents v dd supply voltage (v ddmin , v ddmax ) pic16lf145x 1.80 2.70 ? ? 3.60 3.60 v v fosc <= 16 mhz fosc <= 48 mhz pic16f145x 2.30 2.70 ? ? 5.50 5.50 v v fosc <= 16 mhz fosc <= 48 mhz v pew read/write and row erase operations v ddmin ?v ddmax v v be bulk erase operations 2.7 ? v dd max. v i ddi current on v dd , idle ? ? 1.0 ma i ddp current on v dd , programming ? ? 3.0 ma i pp v pp current on mclr /v pp ? ? 600 a v ihh high voltage on mclr /v pp for program/verify mode entry 8.0 ? 9.0 v t vhhr mclr rise time (v il to v ihh ) for program/verify mode entry ??1.0 s i/o pins v ih (icspclk, icspdat, mclr /v pp ) input high level 0.8 v dd ??v v il (icspclk, icspdat, mclr /v pp ) input low level ? ? 0.2 v dd v v oh icspdat output high level v dd -0.7 v dd -0.7 v dd -0.7 ??v i oh = 3.5 ma, v dd = 5v i oh = 3 ma, v dd = 3.3v i oh = 2 ma, v dd = 1.8v v ol icspdat output low level ?? v ss +0.6 v ss +0.6 v ss +0.6 v i oh = 8 ma, v dd = 5v i oh = 6 ma, v dd = 3.3v i oh = 3 ma, v dd = 1.8v v bor brown-out reset voltage borv = 0 (high trip) 2.55 2.30 2.70 2.40 2.85 2.55 v v pic16f145x pic16lf145x borv = 1 (low trip) 1.80 1.90 2.05 v pic16(l)f145x programming mode entry and exit t ents programing mode entry setup time: icspclk, icspdat setup time before v dd or mclr 100 ? ? ns t enth programing mode entry hold time: icspclk, icspdat hold time after v dd or mclr 250 ? ? s serial program/verify t ckl clock low pulse width 100 ? ? ns t ckh clock high pulse width 100 ? ? ns t ds data in setup time before clock 100 ? ? ns t dh data in hold time after clock 100 ? ? ns t co clock to data out valid (during a read data command) 0 ? 80 ns t lzd clock to data low-impedance (during a read data command) 0 ? 80 ns t hzd clock to data high-impedance (during a read data command) 0 ? 80 ns t dly data input not driven to next clock input (delay required between command/data or command/ command) 1.0 ? ? s note 1: externally timed writes are not support ed for configuration and calibration bits.
? 2011-2012 microchip technology inc. advance information ds41620c-page 33 pic16(l)f145x 8.1 ac timing diagrams figure 8-1: programming mode entry ? v dd first figure 8-2: programming mode entry ? v pp first figure 8-3: programming mode exit ? v pp last figure 8-4: programming mode exit ? v dd last t erab bulk erase cycle time ? ? 5 ms t erar row erase cycle time ? ? 2.5 ms t pint internally timed programming operation time ? ? ? ? 2.5 5 ms ms program memory configuration words t pext externally timed programming pulse 1.0 ? 2.1 ms note 1 t dis time delay from program to compare (hv discharge time) 300 ? ? s t exit time delay when exiting program/verify mode 1 ? ? s note 1: externally timed writes are not support ed for configuration and calibration bits. table 8-1: ac/dc characteristics timing requirements for program/verify ac/dc characteristics standard operating conditions production tested at 25c sym. characteristics min. typ. max. units conditions/comments v pp t enth v dd t ents icspdat icspclk v ihh v il t enth icspdat icspclk v dd t ents v pp v ihh v il t exit v pp v dd icspdat icspclk v ihh v il t exit v pp v dd icspdat icspclk v ihh v il
pic16(l)f145x ds41620c-page 34 advance information ? 2011-2012 microchip technology inc. figure 8-5: clock and data timing figure 8-6: write comm and-payload timing figure 8-7: read command-payload timing as icspclk t ckh t ckl t dh t ds icspdat output t co icspdat icspdat icspdat t lzd t hzd input as from input from output to input to output 12 3 4 5 6 1 2 15 16 x 0 lsb msb 0 t dly command next command payload icspclk icspdat x x x x x 1 2 3 4 5 6 1 2 15 16 x t dly command next command payload icspclk icspdat x x x x x (from programmer) lsb msb 0 icspdat (from device) x
? 2011-2012 microchip technology inc. advance information ds41620c-page 35 pic16(l)f145x figure 8-8: lvp entry (powered) figure 8-9: lvp entry (powering up) t ckl t ckh 33 clocks 0 1 2 ... 31 t dh t ds t enth lsb of pattern msb of pattern v dd mclr icspclk icspdat t ents t ckh t ckl 33 clocks note 1: sequence matching can start with no edge on mclr first. 0 1 2 ... 31 t dh t ds t enth lsb of pattern msb of pattern v dd mclr icspclk icspdat
pic16(l)f145x ds41620c-page 36 advance information ? 2011-2012 microchip technology inc. appendix a: revision history revision a (12/2011) original release of this document. revision b (04/2012) added pic16(l)f1454 devices; removed pic16(l)f1458 devices; removed figure 3-1; updated table 3-1 and register 3-4; updated figures 4-1, 4-2 and 4-3; update d table 4-3 and table 7-1; other minor corrections. revision c (07/2012) revised example 7-4 checksum.
? 2011-2012 microchip technology inc. advance information ds41620c-page 37 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are register ed trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2011-2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620764152 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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